Welcome to AIRI5C Base Core’s documentation!

Contents:

• AIRISC User Guide
• Target Audience
• Introduction
  • Compliance with the RISC-V specification
  • AIRISC architecture overview
• Memory map
• AIRISC Core Complex
  • Configuration
  • List of AIRISC Core Complex top level ports
  • Instruction set extensions
  • Standard peripherals
  • System-Bus
• AIRISC architecture in detail
  • Pipeline
  • PCPI-Interface
  • Privilege Mode
  • Interrupts
  • Exceptions
  • Debug Support
• First steps with the virtual prototype
  • Prerequisite for the commissioning of the virtual prototype
  • Commissioning of the virtual prototype
• AIRISC on a FPGA - Quickstart
  • Prerequisite for bitstream generation and FPGA deployment
  • Commissioning on the Digilent Nexys Video FPGA Board
  • Commissioning on the Digilent Arty-A7 FPGA Board
• Software development on the AIRISC
  • Software prerequisite for software development for AIRISC
  • Other Prerequisite for software development
  • Components of the software development and debugging setup
  • Install IDE and the toolchain
  • Board Support Package (BSP)
  • Connection of the Olimex JTAG Adapter (Arty-A7 only)
  • OpenOCD
  • GDB
  • Eclipse
  • Test and validation
  • Hello World
  • Benchmarking
  • Reference portings

Indices and tables

• Index

• Module Index

• Search Page